1. Field of the Invention
The present invention relates to a semiconductor device having complementary field effect transistors and a method for manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a circuit diagram illustrating an example of SRAMs comprising six MOS transistors.
Namely, the SRAM includes two CMOS invertors comprising p-channel load transistors Q.sub.1 and Q.sub.2 and n-channel drive transistors Q.sub.3 and Q.sub.4 respectively.
The gates of the p-channel load transistor Q.sub.1 and the n-channel drive transistor Q.sub.3 forming one of the CMOS invertors are connected to the drain of the n-channel drive transistor Q.sub.4 of the other of the CMOS invertors respectively. Also, the gates of the p-channel load transistor Q.sub.2 and the n-channel drive transistor Q.sub.4 forming the other of the CMOS invertors are connected to the drain of the n-channel drive transistor Q.sub.3 of the one of the CMOS invertors respectively in the same manner. Furthermore, the drains of the two drive transistors Q.sub.3 and Q.sub.4 are connected respectively to a bit line BL and an inverted bit line BL through the two source/drains of n-channel transfer transistors Q.sub.5 and Q.sub.6. The term "source/drain" designates an appropriate element functioning as either of a source and a drain and is utilized hereinbelow in this sense.
Furthermore, a voltage Vcc is applied to the sources of the two p-channel load transistors Q.sub.1 and Q.sub.2 while a voltage Vss is applied to the sources of the two drive transistors Q.sub.3 and Q.sub.4. The gates of the two transfer transistors Q.sub.5 and Q.sub.6 are connected to a word line WL.
The horizontal configuration of the above SRAM is described, for example, in (1) THOMAS E. TANG et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.ED-34, No.3, March 1987, pp.682-688.
The semiconductor device described therein comprises first and second p-type transistors T.sub.1 and T.sub.2, serving as the load transistors Q.sub.1 and Q.sub.2, formed within an approximately "C"-shaped first active region 101 and first to forth n-type transistors T.sub.3 to T.sub.6, serving as the drive transistors Q.sub.3 and Q.sub.4 and the transfer transistors Q.sub.5 and Q.sub.6, formed within the four straight portions of "L"-shaped second and third active regions 102 and 103 as illustrated in FIG. 2.
The gate electrodes of the first p-type transistor T.sub.1 and the first-n-type transistor T.sub.3 are formed from a first conductive pattern 104 serving as a interconnection. Also, the gate electrodes of the second p-type transistor T.sub.2 and the second n-type transistor T.sub.4 are formed from a second conductive pattern 105 serving as a interconnection.
The drain region of the first p-type transistor T.sub.1 is connected to the drain region of the first n-type transistor T3 through a third conductive pattern 106. Furthermore, the drain regions of the second p-type transistor T.sub.2 and the second n-type transistor T.sub.4 are connected to each other through a fourth conductive pattern 107.
A couple of CMOS invertors are thus formed by this configuration.
Also, a interconnection 104 a extending from the first conductive pattern 104 is connected to the fourth conductive pattern 107. Furthermore, the second conductive pattern 105 is connected to the third conductive pattern 106 in the same manner. The CMOS invertors are cross-coupled by this structure. The word line WL passing through the second and third active regions 102 and 103 serves also as the gate electrodes of third and fourth n-type transistors T.sub.5 and T.sub.6.
Meanwhile, p-type impurity diffusion layers are formed in the both sides of the gate electrodes within the first active region 101, and n-type impurity diffusion layers are formed in the both sides of the gate electrodes within the second active region 102 and the third active region 103. Furthermore, the source/drain regions of the third and fourth n-type transistors T.sub.5 and T.sub.6, which are not connected to the first and second n-type transistors T.sub.3 and T.sub.4, are connected to bit lines which are not shown in this figure.
In the technical field, it has been attempted to fabricate the first p-type transistors T.sub.1 and T.sub.2 as surface channel type transistors in order to suppress the short channel effect of the p-type transistors T.sub.1 and T.sub.2. In this case, the gate electrodes of the p-type transistors T.sub.1 and T.sub.2 are usually formed of a p-type impurity doped silicon.
Accordingly, the gate electrode for making connection between a p-type transistor and an n-type transistor is formed as a dual gate structure comprising a p-type impurity diffusion region and an n-type impurity diffusion region formed in a silicon layer. These regions have to be connected by means of a metallic material or silicide on the both sides of the boundary between the p-type impurity diffusion region and the n-type impurity diffusion region. To this end, a p-type impurity and an n-type impurity are introduced in a separate manner and the p-type impurity diffusion region and the n-type impurity diffusion region are connected by means of silicide.
The dual gate structure is described in (2) Wen-Hsing Chang et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 39, No. 4, APRIL 1992, pp. 959-966 and (3) Bijan Davari et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 39, No. 4, APRIL 1992, pp. 967-975.
However, in order to improve the integration level of semiconductor devices, it is required to decrease the area of the silicide at the boundary in the dual gate structure for fining the dual gate structure much more. This has not been discussed yet.
Meanwhile, as fining semiconductor devices, the accuracy of alignment of contact holes, through which connection of bit lines and interconnections for supplying electric power is made, must be improved. The margin of the alignment may be procured, for example, by providing pad layers on the source regions and the drain regions of MOS transistors, on which connection to bit lines and power lines is made by the so-called self-aligned contact. This technique is described in (4) Japanese Patent Published Application No.Hei2-2139 corresponding to U.S. patent application Ser. No.128,834, filed on Dec. 4, 1987.
However, it is not permitted to grow a metallic film for providing the pad layer in the position of an opening described in the document (4) in the condition that the above described silicide layer is exposed at the surface of the gate because short current paths are formed among the gate and the source/drain.